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Additional info for Programming the Cell Broadband Engine Architecture: Examples and Best Practices
This table is likely to change with future products. Most of the items in the table are described in detail in Chapter 4, “Cell Broadband Engine programming” on page 75. E. features as seen from a programmer’s perspective Good Not so good Large register file DMA (memory latency hiding)a DMA latency Element interconnect bus (EIB) bandwidth b Memory performance Memory size Single-instruction, multiple-data (SIMD)c Scalar performance (scalar on vector) Local storage (latency/bandwidth) Local storage (limited size) Eight Synergistic Processor Element (SPE) per processor (high level of achievable parallelism) Power Processor Element (PPE) performance Nonuniform memory access (NUMA; good scaling) Symmetric multiprocessor (SMP) scaling Branching Single precision floating point Double precision floating pointd a.
HEs usually run a full operating system and submit work to the specialized processes that run in the AEs. E. programs. To demonstrate the versatility of the CBEA, a variety of application-oriented libraries are included, such as the following libraries: Fast Fourier Transform (FFT) Image processing Software managed cache Game math Matrix operation Multi-precision math Synchronization Vector Additional examples and demonstrations show how you can exploit the on-chip computational capacity. Chapter 2.
E. system. E. processor, including the PPE, SPEs, interface bus, and memory and I/O controllers. E. performance monitoring unit (PMU) for counting these events. E. Performance Debug Tool (PDT) provides programmers with a means of analyzing the execution of such a system and tracking problems in order to optimize execution time and utilization of resources. E. board with two PPEs that share the main memory, run under the same (Linux) operating system, and share up to 16 SPEs. The PDT also enables event tracing on the Hybrid-x86.